This invention relates to a semiconductor integrated circuit device, and more particularly to a technique which will be useful when applied to a semiconductor integrated circuit device having a resistance element formed by a semiconductor region.
The inventor of the present invention has now been developing a semiconductor integrated circuit device employing a gate array system. The semiconductor integrated circuit device employing this gate array system can form predetermined logic circuits and memory circuits by a plurality of layers of wirings disposed inside, and between, basic cells. The semiconductor integrated circuit device employing the gate array system can form other kinds of logic circuits and memory circuits by merely changing the wiring patterns of the wirings of the plurality of layers described above. In other words, the gate array system has the characterizing feature in that a wide variety of semiconductor integrated circuit devices can be formed within a short period.
The semiconductor integrated circuit device employing the gate array system described above is a high performance hybrid semiconductor integrated circuit device including bipolar transistors and complementary MISFETs (CMOS) in mixture inside the same substrate. This hybrid semiconductor integrated circuit device is generally referred to as "Hi BiCMOS" (High performance Bipolar CMOS).
The bipolar transistor described above is of an npn type of a vertical structure consisting of an n-type emitter region, a p-type base region and an n-type collector region. The n-type collector region consists of an n-type epitaxial layer having a low impurity concentration, a buried type semiconductor region for reducing the collector resistance and a potential pick-up semiconductor region for picking up a collector current onto the surface of the substrate. The potential pick-up semiconductor region is formed by deeply diffusing thermally an n-type impurity from the surface of the substrate in order to bring its bottom surface into contact with the buried type semiconductor region. Each of these buried type semiconductor region and potential pick-up semiconductor region has a high impurity concentration. The p-type base region is formed on the main planar portion of the epitaxial layer and the n-type emitter region is formed on the main planar portion of the p-type base region.
Among the complementary MISFETs described above, the p-channel MISFET is composed of a channel formation region, a gate insulator film, a gate electrode, a p-type source region and a drain region. Similarly, the n-channel MISFET is composed of the channel formation region, the gate insulator film, the gate electrode, the n-type source region and the drain region.
Incidentally, the hybrid semiconductor integrated circuit device described above is disclosed, for example, in "Nikkei Electronics", Mar. 10, 1986, published by Nikkei-McGraw Hill Co., pp. 199.about.217, and the Bipolar-CMOS gate array, in "Nikkei Electronics", Aug. 12, 1985, pp. 187.about.195.